One way to increase the performance of a personal computer system is to replace the microprocessor in the system with a higher speed microprocessor operating on a higher clock rate, preferably with a cache memory and optionally, on a local bus, high speed memory and certain high speed peripherals such as video display controllers. Other peripheral circuits such as direct memory access (DMA), floppy and hard disk controllers, interrupt controllers and timers of the computer system may be accessed at the clock rate of the original microprocessor clock. Although replacing all of the peripheral circuits in the computer system with circuits which can operate at the new higher speed would yield maximum performance, the cost would be high and many of the higher speed circuits would achieve only small performance increases.
Therefore it is cost effective to replace only those parts of the computer system which give the highest increase in performance for the cost.
In accordance with one prior an proposal, a clock signal for the operation of a high speed replacement microprocessor is generated using a high speed free running oscillator independent of the clock of the slow speed system board. To perform data transfers with the slow speed computer system board, the signals going to the system board are first synchronized to the microprocessor clock of the system board, and then the returning signals are synchronized to the high clock frequency of the replacement microprocessor. However, this double synchronization process for access to the slower peripheral circuits can impose a severe performance penalty. Providing that the ratio of new to original microprocessor clock rates combined with the hit ratio of the cache or high speed local memory are sufficient, the performance will increase, but the increase would be greater if some of the synchronizing delays can be reduced or eliminated. In cases where the clock ratio is small and/or the cache or local memory hit ratio is small, a reduction in performance compared to the original computer system can be expected due to the synchronizing delays.
Other solutions have switched the replacement microprocessor clock rate from the new higher speed to the clock rate of the slow speed system board for data transfers with the slow speed system board, but with the advent of microprocessors with clock doubling or tripling on chip, it is often necessary to have a stable frequency for the new microprocessor clock. In other cases buffering on the microprocessor chip of external data write transfers causes a performance penalty when the microprocessor clock is slowed during these transfers to the slower system peripherals.
In accordance with other proposals, the clock signal for the operation of the replacement microprocessor is derived from the clock system of the slow speed system. However, with certain slow speed systems the clock speed may switch between two rates, thereby compounding the difficulty of providing a stable clock signal for the operation of the high speed replacement microprocessor.